The present invention relates to a method for fabricating capacitor electrodes. The present invention relates in particular to a method for fabricating capacitor electrodes in trenches, as are used, for example, in large-scale integrated memory components.
To be able to reproducibly read the charge which is stored in a storage capacitor of a memory cell, the capacitance of the storage capacitor should be at least 30 fF. At the same time, the lateral extent of the capacitor is being constantly reduced, in order to be able to increase the storage density. These contrary demands imposed on the capacitor of the memory cells lead to increasingly complex structuring of the capacitor (xe2x80x9ctrench capacitorsxe2x80x9d, xe2x80x9cstack capacitorsxe2x80x9d, xe2x80x9ccrown-shaped capacitorsxe2x80x9d), in order to be able to provide a sufficient capacitor surface area despite the decreasing lateral extent of the capacitor.
In order, in stack capacitors or crown-shaped capacitors, to be able to ensure that the capacitance of the storage capacitor remains at least constant even as the lateral extent of the storage capacitor decreases, capacitor electrodes made from HSG (hemispherical grain) silicon are frequently used. The use of HSG silicon is a method which has been tried and tested and is well known in the semiconductor industry in order to increase the surface area of capacitor electrodes, in order, in this way, to raise the overall capacitance of the capacitor. Special deposition methods and/or special temperature treatments are used to produce small silicon grains, with the size of a few tens to hundreds of nm, on the capacitor surface. The silicon grains mean that the capacitor electrodes acquire a roughened and therefore enlarged surface area, which leads to increased capacitance of the storage capacitors.
Methods for producing HSG (hemispherical grain) silicon are described, for example, in U.S. Pat. Nos. 5,858,852, 5,858,837, and 5,723,379. Methods for increasing the capacitance of capacitors using HSG silicon are described, for example, in U.S. Pat. Nos. 5,877,061, 5,872,033 and 5,972,771. In the methods described in U.S. Pat. Nos. 5,872,033 and 5,972,771, the HSG grains undergo a further treatment by etching, so that the distance between the HSG grains is increased. In this way, the electrode surface area can be increased in a controlled manner. Unfortunately, the abovementioned methods also entail a range of drawbacks. The use of HSG grains as a significant constituent of the capacitor electrodes leads to an increased leakage current in the capacitor in question. Furthermore, the HSG grains on the electrode surface may lead to short-circuits between adjacent capacitors.
In addition to stack capacitors and crown-shaped capacitors, what are known as trench capacitors are also used, in order to be able to ensure that the capacitance of the storage capacitor remains at least constant while the lateral extent of the storage capacitor becomes ever smaller. While in the case of memory cells with stack capacitors or crown-shaped capacitors the storage capacitor is arranged above the select transistors, in memory cells with trench capacitors the storage capacitor is arranged below the select transistors in the semiconductor substrate.
The increasing integration density of the memory components in memory cells with trench capacitors leads to constantly falling trench diameters. In order, despite increasing trench diameters, to ensure a capacitor capacitance which remains approximately constant from generation to generation, it has hitherto been possible to increase the depth of the trench within certain limits. However, this direct route is encountering technological and economic limits. Firstly, etching processes which make it possible to produce ever higher aspect ratios are required in order to make the trench deeper. This already presents limits which are inherent to the process. Secondly, even if such etching processes exist, the longer etching time beyond a certain etching depth limits the economic viability of the procedure.
Using HSG silicon in trench capacitors in order to increase the electrode surface area with stack capacitors or crown-shaped capacitors is one option for increasing the electrode surface area. However, the growth of HSG silicon on the side walls of the trenches noticeably reduces the trench diameter. Consequently, considerable problems may arise during the subsequent production of the dielectric layer and the subsequent filling of the trenches with the counterelectrodes. By way of example, the HSG silicon may lead to constrictions within the trenches, preventing further filling of the trench (xe2x80x9ccut-off effectxe2x80x9d).
Therefore, the present invention is based on the object of providing a method for fabricating capacitor electrodes which reduces or completely prevents the drawbacks of the conventional methods. In particular, the object of the present invention is to provide a method for the fabrication of capacitor electrodes in trenches which makes it possible to fabricate trench capacitors of sufficient capacitance without increasing the depth of the trenches.
This object is achieved by the method for fabricating capacitor electrodes described in the independent patent claim 1. Further advantageous embodiments, configurations and aspects of the present invention will emerge from the dependent patent claims, the description and the appended drawings.
The invention provides a method for fabricating capacitor electrodes comprising the following steps:
a) an electrode is provided,
b) at least one sacrificial layer is applied to the electrode;
c) a discontinuous layer is applied to the sacrificial layer,
d) the electrode is structured with the aid of the discontinuous layer and the sacrificial layer, so that an electrode with an enlarged surface is produced.
With the aid of the method according to the invention, it is possible for the roughness of the surface of the discontinuous layer to be substantially transferred to the surface of the electrode. The electrode consequently acquires a microstructured surface, the area of which can be increased by more than 25%, preferably by more than 50%, and particularly preferably by more than 100%. The discontinuous layer is used to locally mask the electrode surface or the sacrificial layer. Subsequent structuring processes, such as for example wet-chemical and/or plasma-assisted etching processes, nitriding or oxidation processes, make it possiblexe2x80x94working on the basis of micromasking effectsxe2x80x94to significantly roughen the electrode surface and thereby to increase the electrode surface area.
Unfortunately, it is not possible for every discontinuous layer to be applied to any desired electrode surface without difficulty. For example, it is difficult for HSG silicon with sufficient roughness, which is preferably used as the discontinuous layer, to be applied to monocrystalline silicon. However, using a sacrificial layer provides a surface to which the discontinuous layer can be successfully applied. Accordingly, there is a wider selection of materials which can be used as the electrode material. Furthermore, during the actual microstructuring of the electrode surface, the sacrificial layer ensures sufficient selectivity with respect to the electrode surface.
Furthermore, the method according to the invention has the advantage that the discontinuous layer is either removed automatically during the structuring of the electrode or can be removed using an additional process step after the structuring of the electrodes. Therefore, the overall result is the geometric surface structure of the discontinuous layer without having to keep space reserved for the discontinuous layer itself. This is important in particular for the production of electrodes in trench capacitors, since in such capacitors the discontinuous layer would constrict the capacitor trench. Furthermore, the method according to the invention has the advantage that the electrode material is no longer restricted to the material of the discontinuous layer, for example HSG silicon. For example, it is now also possible to use single-crystal silicon for what is known as a xe2x80x9crough silicon capacitorxe2x80x9d, so that the leakage current properties of the capacitor are significantly improved.
According to a preferred embodiment, the discontinuous layer is deposited in such a way that adjacent grains or islands fuse together and thereby form larger cohesive regions, between which smaller uncovered openings remain. As an alternative, the discontinuous layer may be deposited in such a way that adjacent grains or islands are arranged substantially separately from one another. Which of these alternatives is used depends substantially on whether the structure of the discontinuous layer is to be transferred positively or negatively to the electrode. Furthermore, it is preferable if an HSG layer, in particular HSG silicon or HSG-SiGe (silicon/germanium), is used as the discontinuous layer.
According to a preferred embodiment, the sacrificial layer is structured to form a mask which is used for structuring the electrode. In this case, it is preferable in particular if the sacrificial layer is structured selectively with respect to the electrode and/or selectively with respect to the discontinuous layer. Wet-chemical or a dry-chemical method is preferably used to structure the sacrificial layer.
According to a further preferred embodiment, an oxide layer or nitride layer or an oxide/nitride double layer is used as the sacrificial layer.
Furthermore, it is preferable if the discontinuous layer is nitrided. It is also preferable if a nitride layer is used as the sacrificial layer and the discontinuous layer is at least partially oxidized before the structuring of the sacrificial layer.
Furthermore, it is preferable if the electrode is structured by isotropic etching or by oxidation with subsequent isotropic etching. In this case, it is particularly preferable if oxide regions, which subsequently serve as an etching mask for the isotropic etching of the electrode, are produced in the electrode with the aid of a nitride mask.
According to a further preferred embodiment, an oxide layer is used as the sacrificial layer and a nitriding treatment is carried out, so that nitride regions are produced in the electrode. In this case, it is particularly preferred if the electrode with the nitride regions is subsequently oxidized and is structured by isotropic oxide etching. Furthermore, it is preferable if the nitride regions in the electrode surface are used as a mask for isotropic etching.
According to a further preferred embodiment, monocrystalline or polycrystalline silicon is used as the material for the electrode.